The present invention relates to a test structure region on a wafer and, in particular to a test structure region which can be arranged between two integrated circuits on a wafer.
Integrated circuits are produced on monocrystaline silicon discs, so-called wafers. Since the area available on a wafer is considerably larger than the area of an integrated circuit, a plurality of integrated circuits, which for the most part are identical, are accommodated on each wafer produced. During the production of integrated circuits, photolithographic processes are used repeatedly, in which the wafer is exposed through a mask. By means of this illumination operation, for example, structures belonging to the integrated circuit and that are to be etched out are defined in a photoresist. For rationalization reasons, for the most part a number of masks for a number of integrated circuits located beside one another are arranged on a lithographic film and exposed together. The integrated circuits exposed together in this way are referred to as a reticle. Between the individual integrated circuits there is an interspace, in which the finished integrated circuits can be separated from one another by sawing or etching. The interspace is removed chemically or mechanically.
However, before the separation operation, the interspace is used for test purposes by test structures that are provided on the coherent masks for producing a reticle. The test structures between the actual regions of the integrated circuits are exposed at the same time and fill up the interspace between the individual integrated circuits.
These test structures normally comprise contact areas (so-called pads) and test components, mostly transistors, which are arranged between the contact areas. A test component in each case is located between two contact areas.
Following the production of the integrated circuits on a wafer, contact can be made with these test regions and the operability of the test components arranged on them, for example the transistors, can be checked. The operability of the transistors supplies a quite reliable image of the quality of the production process of the integrated circuits on the respective wafer. It can be assumed that problems which manifest themselves in the test regions are also present in the integrated circuits, so that the latter can be separated out early, before their unoperability is established in a significantly more complicated test process that follows this general test.
With increasing integration density of the integrated circuits, in particular in the case of memory components such as DRAM (Dynamic Random Access Memory), SDRAM (Synchronous Dynamic Random Access Memory), RAMBUS, or EDRAM (Enhanced Dynamic Random Access Memory), however, the problem arises that an ever increasing number of functional elements are arranged on a specific area of the wafer. In contrast, the packing density in the test regions located between the integrated circuits cannot be increased substantially, since the majority of the area which is available is occupied by the contact areas, whose size can not be practically reduced. Therefore, with increasing integration density, the ratio between the number of test components and the number of functional components decreases. This decrease in the number of testable individual structures, and the associated loss of information, in particular in developing and in starting production of a new product, was tolerated in the prior art, but was unsatisfactory to a high degree.
Published European Patent Application EP 0 133 955 A1 shows a test structure for identifying semiconductor chips, in which parallel-connected components are provided between two connection areas. Following a test, one or more of the components is severed in order to identify the semiconductor chip. Use may be made of connection areas which are not accessible during normal operation. A threshold switch, for example a thick oxide transistor, prevents the test structure from having any influence on the otherwise connected circuit parts of the semiconductor chip.
U.S. Pat. No. 5,942,766 shows a different test structure for measuring RF parameters of integrated circuits arranged on a wafer. The test structures are arranged between the integrated circuits. They each comprise a connection area which serves as an input, output, or ground for the test element.
It is accordingly an object of the invention to provide a test structure region on a wafer which overcomes the above-mentioned disadvantageous of the prior art apparatus of this general type, and which, in particular, provides an increased number of testable individual structures, or test components relative to the chip area of the integrated circuits.
With the foregoing and other objects in view there is provided, in accordance with the invention a test structure that includes a wafer, or a test structure region having a plurality of sets of at least two transistors. Each one of the at least two transistors of the plurality of the sets defines a test component. The test structure includes a plurality of contact areas disposed on the wafer. The at least two transistors of each one of the plurality of the sets are disposed between and are connected to a respective pair of adjacent ones of the plurality of the contact areas for receiving a voltage that can be applied to the respective pair of adjacent ones of the plurality of the contact areas. The test structure also includes a plurality of additional contact areas disposed on the wafer. One of the at least two transistors of each one of the plurality of the sets includes a gate connection connected to a respective one of the plurality of the additional contact areas for receiving a switching current. Another one of the at least two transistors of each one of the plurality of the sets includes a gate connection connected to an area selected from the group consisting of the respective one of the plurality of the additional contact areas for receiving the switching current and another respective one of the plurality of the additional contact areas for receiving another switching current such that the at least two transistors of each one of the sets can be switched on alternately from each other.
In other words, the invention provides a test structure region on a wafer having contact areas for applying voltages and test components between the contact areas, in this test structure region at least two test components are arranged between two adjacent contact areas in each case and being connected to the adjacent contact areas, so that a voltage can be applied to the test components via the contact areas.
The gate connections of the transistors are connected to further contact areas in order to supply a switching current. As a result, the gate connections of the transistors can be driven independently of one another, and the transistors can be tested independently of one another.
This increases the number of testable test components between the contact areas. Hitherto, it was assumed that it was only expedient to place one test component between two contact areas in each case.
The test components are transistors. These can, for example, be connected by their source regions to one adjacent contact area and by drain regions to the other adjacent contact area.
The gate regions can, for example, also run via a common pole 20 which, during the testing of the test structure region, can be switched on and off via special contact areas provided for the purpose.
In accordance with an added feature of the invention, the gate connections of the transistors can be driven separately from one another, in order to change over alternately between the transistors by a respective current pulse. The gate connections are each connected via a corresponding line to a respective further contact area.
As already explained, the invention is preferably directed toward test structure regions which are arranged between two integrated circuits. However, the invention is also suitable for providing test structure regions in other regions of integrated circuits and, in particular in regions that are not removed after the test. In particular in the case of highly complex chips, for example processors, which occupy a comparatively large chip area, it may be expedient to provide test structure regions of the type according to the invention in the interior of each chip area as well.
In accordance with a concomitant feature of the invention, the test structure region can preferably have a width of 50 to 200 xcexcm. The width is determined critically by the size of the contact areas, which may be arranged in a row, and which define the width of the space available for the arrangement of test components.
Other features which are considered as characteristic for the invention are set forth in the appended claims.
Although the invention is illustrated and described herein as embodied in a test structure in an integrated semiconductor, it is nevertheless not intended to be limited to the details shown, since various modifications and structural changes may be made therein without departing from the spirit of the invention and within the scope and range of equivalents of the claims.
The construction and method of operation of the invention, however, together with additional objects and advantages thereof will be best understood from the following description of specific embodiments when read in connection with the accompanying drawings.